/*
 * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */


#ifndef HPM_PIXELMUX_H
#define HPM_PIXELMUX_H

typedef struct {
    __RW uint32_t PIXMUX;                      /* 0x0: pixel path mux register */
    __RW uint32_t DSI_SETTING[2];              /* 0x4 - 0x8: DSI0 config register */
    __RW uint32_t MISC;                        /* 0xC: common register */
    __RW uint32_t GPR_WR_D0;                   /* 0x10: gpr write-read register 0 */
    __RW uint32_t GPR_WR_D1;                   /* 0x14: gpr write-read register 1 */
    __RW uint32_t GPR_WR_D2;                   /* 0x18: gpr write-read register 2 */
    __RW uint32_t GPR_WR_D3;                   /* 0x1C: gpr write-read register 3 */
    __RW uint32_t GPR_WR_D4;                   /* 0x20: gpr write-read register 4 */
    __RW uint32_t GPR_WR_D5;                   /* 0x24: gpr write-read register 5 */
    __RW uint32_t GPR_WR_D6;                   /* 0x28: gpr write-read register 6 */
    __RW uint32_t GPR_WR_D7;                   /* 0x2C: gpr write-read register 7 */
    __RW uint32_t GPR_WR_D8;                   /* 0x30: gpr write-read register 8 */
    __RW uint32_t GPR_WR_D9;                   /* 0x34: gpr write-read register 9 */
    __R  uint32_t GPR_RO_D0;                   /* 0x38: gpr read-only register 0 */
    __R  uint32_t GPR_RO_D1;                   /* 0x3C: gpr read-only register 1 */
    __R  uint32_t GPR_RO_D2;                   /* 0x40: gpr read-only register 2 */
    __R  uint32_t GPR_RO_D3;                   /* 0x44: gpr read-only register 3 */
    __R  uint32_t GPR_RO_D4;                   /* 0x48: gpr read-only register 4 */
    __R  uint32_t GPR_RO_D5;                   /* 0x4C: gpr read-only register 5 */
    __R  uint32_t GPR_RO_D6;                   /* 0x50: gpr read-only register 6 */
    __R  uint32_t GPR_RO_D7;                   /* 0x54: gpr read-only register 7 */
    __R  uint32_t GPR_RO_D8;                   /* 0x58: gpr read-only register 8 */
    __R  uint32_t GPR_RO_D9;                   /* 0x5C: gpr read-only register 9 */
    __RW uint32_t GPR_WR1_CLR_D0;              /* 0x60: gpr write1 set/no-write clr register */
} PIXELMUX_Type;


/* Bitfield definition for register: PIXMUX */
/*
 * RGB_EN (RW)
 *
 * RGB pixel bus enable
 */
#define PIXELMUX_PIXMUX_RGB_EN_MASK (0x20000000UL)
#define PIXELMUX_PIXMUX_RGB_EN_SHIFT (29U)
#define PIXELMUX_PIXMUX_RGB_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_EN_SHIFT) & PIXELMUX_PIXMUX_RGB_EN_MASK)
#define PIXELMUX_PIXMUX_RGB_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_EN_MASK) >> PIXELMUX_PIXMUX_RGB_EN_SHIFT)

/*
 * RGB_SEL (RW)
 *
 * RGB pixel bus selection
 * 1: LCDC1
 * 0: LCDC0
 */
#define PIXELMUX_PIXMUX_RGB_SEL_MASK (0x10000000UL)
#define PIXELMUX_PIXMUX_RGB_SEL_SHIFT (28U)
#define PIXELMUX_PIXMUX_RGB_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_SEL_SHIFT) & PIXELMUX_PIXMUX_RGB_SEL_MASK)
#define PIXELMUX_PIXMUX_RGB_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_SEL_MASK) >> PIXELMUX_PIXMUX_RGB_SEL_SHIFT)

/*
 * GWC1_EN (RW)
 *
 * GWC1 pixel bus enable
 */
#define PIXELMUX_PIXMUX_GWC1_EN_MASK (0x8000000UL)
#define PIXELMUX_PIXMUX_GWC1_EN_SHIFT (27U)
#define PIXELMUX_PIXMUX_GWC1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_EN_SHIFT) & PIXELMUX_PIXMUX_GWC1_EN_MASK)
#define PIXELMUX_PIXMUX_GWC1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_EN_MASK) >> PIXELMUX_PIXMUX_GWC1_EN_SHIFT)

/*
 * GWC1_SEL (RW)
 *
 * GWC1 pixel bus selection
 * 1: LCDC1
 * 0: LCDC0
 */
#define PIXELMUX_PIXMUX_GWC1_SEL_MASK (0x4000000UL)
#define PIXELMUX_PIXMUX_GWC1_SEL_SHIFT (26U)
#define PIXELMUX_PIXMUX_GWC1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC1_SEL_MASK)
#define PIXELMUX_PIXMUX_GWC1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) >> PIXELMUX_PIXMUX_GWC1_SEL_SHIFT)

/*
 * GWC0_EN (RW)
 *
 * GWC0 pixel bus enable
 */
#define PIXELMUX_PIXMUX_GWC0_EN_MASK (0x2000000UL)
#define PIXELMUX_PIXMUX_GWC0_EN_SHIFT (25U)
#define PIXELMUX_PIXMUX_GWC0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_EN_SHIFT) & PIXELMUX_PIXMUX_GWC0_EN_MASK)
#define PIXELMUX_PIXMUX_GWC0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_EN_MASK) >> PIXELMUX_PIXMUX_GWC0_EN_SHIFT)

/*
 * GWC0_SEL (RW)
 *
 * GWC0 pixel bus selection
 * 1: LCDC1
 * 0: LCDC0
 */
#define PIXELMUX_PIXMUX_GWC0_SEL_MASK (0x1000000UL)
#define PIXELMUX_PIXMUX_GWC0_SEL_SHIFT (24U)
#define PIXELMUX_PIXMUX_GWC0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC0_SEL_MASK)
#define PIXELMUX_PIXMUX_GWC0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) >> PIXELMUX_PIXMUX_GWC0_SEL_SHIFT)

/*
 * LVB_DI1_EN (RW)
 *
 * LVB DI1 pixel bus enable
 */
#define PIXELMUX_PIXMUX_LVB_DI1_EN_MASK (0x800000UL)
#define PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT (23U)
#define PIXELMUX_PIXMUX_LVB_DI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK)
#define PIXELMUX_PIXMUX_LVB_DI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT)

/*
 * LVB_DI1_SEL (RW)
 *
 * LVB DI1 pixel bus selection
 * 1: LCDC1
 * 0: LCDC0
 */
#define PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK (0x400000UL)
#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT (22U)
#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK)
#define PIXELMUX_PIXMUX_LVB_DI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT)

/*
 * LVB_DI0_EN (RW)
 *
 * LVB DI0 pixel bus enable
 */
#define PIXELMUX_PIXMUX_LVB_DI0_EN_MASK (0x200000UL)
#define PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT (21U)
#define PIXELMUX_PIXMUX_LVB_DI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK)
#define PIXELMUX_PIXMUX_LVB_DI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT)

/*
 * LVB_DI0_SEL (RW)
 *
 * LVB DI0 pixel bus selection
 * 1: LCDC1
 * 0: LCDC0
 */
#define PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK (0x100000UL)
#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT (20U)
#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK)
#define PIXELMUX_PIXMUX_LVB_DI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT)

/*
 * DSI1_EN (RW)
 *
 * DSI0 pixel bus enable
 */
#define PIXELMUX_PIXMUX_DSI1_EN_MASK (0x80000UL)
#define PIXELMUX_PIXMUX_DSI1_EN_SHIFT (19U)
#define PIXELMUX_PIXMUX_DSI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_EN_SHIFT) & PIXELMUX_PIXMUX_DSI1_EN_MASK)
#define PIXELMUX_PIXMUX_DSI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_EN_MASK) >> PIXELMUX_PIXMUX_DSI1_EN_SHIFT)

/*
 * DSI1_SEL (RW)
 *
 * DSI0 pixel bus selection
 * 1: LCDC1
 * 0: LCDC0
 */
#define PIXELMUX_PIXMUX_DSI1_SEL_MASK (0x40000UL)
#define PIXELMUX_PIXMUX_DSI1_SEL_SHIFT (18U)
#define PIXELMUX_PIXMUX_DSI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI1_SEL_MASK)
#define PIXELMUX_PIXMUX_DSI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) >> PIXELMUX_PIXMUX_DSI1_SEL_SHIFT)

/*
 * DSI0_EN (RW)
 *
 * DSI1 pixel bus enable
 */
#define PIXELMUX_PIXMUX_DSI0_EN_MASK (0x20000UL)
#define PIXELMUX_PIXMUX_DSI0_EN_SHIFT (17U)
#define PIXELMUX_PIXMUX_DSI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_EN_SHIFT) & PIXELMUX_PIXMUX_DSI0_EN_MASK)
#define PIXELMUX_PIXMUX_DSI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_EN_MASK) >> PIXELMUX_PIXMUX_DSI0_EN_SHIFT)

/*
 * DSI0_SEL (RW)
 *
 * DSI1 pixel bus selection
 * 1: LCDC1
 * 0: LCDC0
 */
#define PIXELMUX_PIXMUX_DSI0_SEL_MASK (0x10000UL)
#define PIXELMUX_PIXMUX_DSI0_SEL_SHIFT (16U)
#define PIXELMUX_PIXMUX_DSI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI0_SEL_MASK)
#define PIXELMUX_PIXMUX_DSI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) >> PIXELMUX_PIXMUX_DSI0_SEL_SHIFT)

/*
 * CAM1_EN (RW)
 *
 * CAM1 pixel bus enable
 */
#define PIXELMUX_PIXMUX_CAM1_EN_MASK (0x80U)
#define PIXELMUX_PIXMUX_CAM1_EN_SHIFT (7U)
#define PIXELMUX_PIXMUX_CAM1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_EN_SHIFT) & PIXELMUX_PIXMUX_CAM1_EN_MASK)
#define PIXELMUX_PIXMUX_CAM1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_EN_MASK) >> PIXELMUX_PIXMUX_CAM1_EN_SHIFT)

/*
 * CAM1_SEL (RW)
 *
 * CAM1 pixel bus selection
 * 111: Reserved
 * 110: LCB1
 * 101: LCB0
 * 100: LCDC1
 * 011: LCDC0
 * 010: CSI1
 * 001: CSI0
 * 000: DVP
 */
#define PIXELMUX_PIXMUX_CAM1_SEL_MASK (0x70U)
#define PIXELMUX_PIXMUX_CAM1_SEL_SHIFT (4U)
#define PIXELMUX_PIXMUX_CAM1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM1_SEL_MASK)
#define PIXELMUX_PIXMUX_CAM1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) >> PIXELMUX_PIXMUX_CAM1_SEL_SHIFT)

/*
 * CAM0_EN (RW)
 *
 * CAM0 pixel bus enable
 */
#define PIXELMUX_PIXMUX_CAM0_EN_MASK (0x8U)
#define PIXELMUX_PIXMUX_CAM0_EN_SHIFT (3U)
#define PIXELMUX_PIXMUX_CAM0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_EN_SHIFT) & PIXELMUX_PIXMUX_CAM0_EN_MASK)
#define PIXELMUX_PIXMUX_CAM0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_EN_MASK) >> PIXELMUX_PIXMUX_CAM0_EN_SHIFT)

/*
 * CAM0_SEL (RW)
 *
 * CAM0 pixel bus selection
 * 111: Reserved
 * 110: LCB1
 * 101: LCB0
 * 100: LCDC1
 * 011: LCDC0
 * 010: CSI1
 * 001: CSI0
 * 000: DVP
 */
#define PIXELMUX_PIXMUX_CAM0_SEL_MASK (0x7U)
#define PIXELMUX_PIXMUX_CAM0_SEL_SHIFT (0U)
#define PIXELMUX_PIXMUX_CAM0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM0_SEL_MASK)
#define PIXELMUX_PIXMUX_CAM0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) >> PIXELMUX_PIXMUX_CAM0_SEL_SHIFT)

/* Bitfield definition for register array: DSI_SETTING */
/*
 * DSI_DATA_ENABLE (RW)
 *
 * DSI pixel data type enable:
 * Bit0: RGB565_CFG1
 * Bit1: RGB565_CFG2
 * Bit2: RGB565_CFG3
 * Bit3: RGB666_CFG1
 * Bit4: RGB666_CFG2
 * Bit5: RGB888
 * Bit6: RGB_10BIT
 * Bit7: RGB_12BIT, no support
 * Bit8: YUV422_12BIT, no support
 * Bit9: YUV422_10BIT, no support
 * Bit10: YUV422_8BIT, no support
 * Bit11:YUV420_8BIT,no support
 * others: Reserved
 */
#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK (0xFFFF0000UL)
#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT (16U)
#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK)
#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT)

/*
 * DSI_DATA_TYPE (RW)
 *
 * DSI input pixel data type:
 * ‘h0: RGB565_CFG1
 * ‘h1: RGB565_CFG2
 * ‘h2: RGB565_CFG3
 * ‘h3: RGB666_CFG1
 * ‘h4: RGB666_CFG2
 * ‘h5: RGB888
 * ‘h6: RGB_10BIT
 * ‘h7: RGB_12BIT, no support
 * ‘h8:YUV422_12BIT,no support
 * ‘h9: YUV422_10BIT, no support
 * ‘ha: YUV422_8BIT, no support
 * ‘hb: YUV420_8BIT,no support
 * ‘hc~’hf: Reserved
 */
#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK (0xFU)
#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT (0U)
#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK)
#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT)

/* Bitfield definition for register: MISC */
/*
 * LVB_DI1_CTL (RW)
 *
 * LVB DI1 optional general purpose control which is usually unused by display
 */
#define PIXELMUX_MISC_LVB_DI1_CTL_MASK (0x2U)
#define PIXELMUX_MISC_LVB_DI1_CTL_SHIFT (1U)
#define PIXELMUX_MISC_LVB_DI1_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI1_CTL_MASK)
#define PIXELMUX_MISC_LVB_DI1_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) >> PIXELMUX_MISC_LVB_DI1_CTL_SHIFT)

/*
 * LVB_DI0_CTL (RW)
 *
 * LVB DI0 optional general purpose control which is usually unused by display
 */
#define PIXELMUX_MISC_LVB_DI0_CTL_MASK (0x1U)
#define PIXELMUX_MISC_LVB_DI0_CTL_SHIFT (0U)
#define PIXELMUX_MISC_LVB_DI0_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI0_CTL_MASK)
#define PIXELMUX_MISC_LVB_DI0_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) >> PIXELMUX_MISC_LVB_DI0_CTL_SHIFT)

/* Bitfield definition for register: GPR_WR_D0 */
/*
 * CSI1_CFG_AP_IF_CHECK_EN (RW)
 *
 * csi1 apb interface parity check enable
 */
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK (0x7C00000UL)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT (22U)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT)

/*
 * CSI1_CFG_AP_IF_INT_EN (RW)
 *
 * csi1 apb interface error interrupt enable
 */
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK (0x200000UL)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT (21U)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT)

/*
 * CSI1_CFG_APB_SLVERROR_EN (RW)
 *
 * csi1 apb interface error check enable
 */
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK (0x100000UL)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT (20U)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK)
#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT)

/*
 * CSI0_CFG_AP_IF_CHECK_EN (RW)
 *
 * csi0 apb interface parity check enable
 */
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK (0x7C000UL)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT (14U)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT)

/*
 * CSI0_CFG_AP_IF_INT_EN (RW)
 *
 * csi0 apb interface error interrupt enable
 */
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK (0x2000U)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT (13U)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT)

/*
 * CSI0_CFG_APB_SLVERROR_EN (RW)
 *
 * csi0 apb interface error check enable
 */
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK (0x1000U)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT (12U)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK)
#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT)

/*
 * DSI1_DPIUPDATECFG (RW)
 *
 * dsi1 dpi update configure
 */
#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK (0x200U)
#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT (9U)
#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK)
#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT)

/*
 * DSI1_DPICOLORM (RW)
 *
 * dsi1 dpi cholor mode control
 */
#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK (0x100U)
#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT (8U)
#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK)
#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT)

/*
 * DSI1_DPISHUTDN (RW)
 *
 * dsi1 dpi shuntdown control
 */
#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK (0x80U)
#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT (7U)
#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK)
#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT)

/*
 * DSI0_DPIUPDATECFG (RW)
 *
 * dsi0 dpi update configure
 */
#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK (0x40U)
#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT (6U)
#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK)
#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT)

/*
 * DSI0_DPICOLORM (RW)
 *
 * dsi0 dpi cholor mode control
 */
#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK (0x20U)
#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT (5U)
#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK)
#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT)

/*
 * DSI0_DPISHUTDN (RW)
 *
 * dsi0 dpi shuntdown control
 */
#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK (0x10U)
#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT (4U)
#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK)
#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT)

/*
 * CSI1_SOFT_RESET_N (RW)
 *
 * csi controller 1 reset, active low
 */
#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK (0x8U)
#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT (3U)
#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK)
#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT)

/*
 * CSI0_SOFT_RESET_N (RW)
 *
 * csi controller 0 reset, active low
 */
#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK (0x4U)
#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT (2U)
#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK)
#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT)

/*
 * DSI1_SOFT_RESET_N (RW)
 *
 * dsi controller 1 reset, active low
 */
#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK (0x2U)
#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT (1U)
#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK)
#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT)

/*
 * DSI0_SOFT_RESET_N (RW)
 *
 * dsi controller 0 reset, active low
 */
#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK (0x1U)
#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT (0U)
#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK)
#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT)

/* Bitfield definition for register: GPR_WR_D1 */
/*
 * JPEG_CTRL (RW)
 *
 * bit0: select cam0;
 * bit1: select cam1;
 * bit2: select jpeg;
 * bit3: select pdma
 */
#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK (0xF000000UL)
#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT (24U)
#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK)
#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT)

/*
 * PDMA_P1_CTRL (RW)
 *
 * bit0: select cam0;
 * bit1: select cam1;
 * bit2: select jpeg;
 * bit3: select pdma
 */
#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK (0xF00000UL)
#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT (20U)
#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK)
#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT)

/*
 * PDMA_P0_CTRL (RW)
 *
 * bit0: select cam0;
 * bit1: select cam1;
 * bit2: select jpeg;
 * bit3: select pdma
 */
#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK (0xF0000UL)
#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT (16U)
#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK)
#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT)

/*
 * LCDC1_P1_CTRL (RW)
 *
 * bit0: select cam0;
 * bit1: select cam1;
 * bit2: select jpeg;
 * bit3: select pdma
 */
#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK (0xF000U)
#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT (12U)
#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK)
#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT)

/*
 * LCDC1_P0_CTRL (RW)
 *
 * bit0: select cam0;
 * bit1: select cam1;
 * bit2: select jpeg;
 * bit3: select pdma
 */
#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK (0xF00U)
#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT (8U)
#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK)
#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT)

/*
 * LCDC0_P1_CTRL (RW)
 *
 * bit0: select cam0;
 * bit1: select cam1;
 * bit2: select jpeg;
 * bit3: select pdma
 */
#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK (0xF0U)
#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT (4U)
#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK)
#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT)

/*
 * LCDC0_P0_CTRL (RW)
 *
 * bit0: select cam0;
 * bit1: select cam1;
 * bit2: select jpeg;
 * bit3: select pdma
 */
#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK (0xFU)
#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT (0U)
#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK)
#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT)

/* Bitfield definition for register: GPR_WR_D2 */
/*
 * TX_PHY0_PORT_PLL_RDY_SEL (RW)
 *
 * tx phy0 port_pll_rdy_sel
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK (0x20000000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT (29U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT)

/*
 * TX_PHY0_RATE_LVDS (RW)
 *
 * tx phy0 rate_lvds
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK (0x18000000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT (27U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT)

/*
 * TX_PHY0_PHY_MODE (RW)
 *
 * tx phy0 phy_mode
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK (0x6000000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT (25U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT)

/*
 * TX_PHY0_REFCLK_DIV (RW)
 *
 * tx phy0 refclk_div
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK (0xF00000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT (20U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT)

/*
 * TX_PHY0_IDDQ_EN (RW)
 *
 * tx phy0 iddq_en
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK (0x80000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT (19U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT)

/*
 * TX_PHY0_RESET_N (RW)
 *
 * tx phy0 reset, active low
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK (0x40000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT (18U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT)

/*
 * TX_PHY0_SHUTDOWNZ (RW)
 *
 * tx phy0 shutdownz, active low
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK (0x20000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT (17U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT)

/*
 * TX_PHY0_BYPS_CKDET (RW)
 *
 * tx phy0 byps_ckdet
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK (0x10000UL)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT (16U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT)

/*
 * TX_PHY0_PLL_DIV (RW)
 *
 * tx phy0 pll_div
 */
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (0x7FFFU)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT (0U)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK)
#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT)

/* Bitfield definition for register: GPR_WR_D3 */
/*
 * TX_PHY0_PLL_CTRL (RW)
 *
 * tx phy0 pll_ctrl
 */
#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK (0xFFFFFFFFUL)
#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT (0U)
#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK)
#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT)

/* Bitfield definition for register: GPR_WR_D4 */
/*
 * TX_PHY0_TXCK_BIST_EN (RW)
 *
 * tx phy0 txck_bist_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK (0x80000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT (31U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT)

/*
 * TX_PHY0_TX3_BIST_EN (RW)
 *
 * tx phy0 tx3_bist_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK (0x40000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT (30U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT)

/*
 * TX_PHY0_TX2_BIST_EN (RW)
 *
 * tx phy0 tx2_bist_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK (0x20000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT (29U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT)

/*
 * TX_PHY0_TX1_BIST_EN (RW)
 *
 * tx phy0 tx1_bist_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK (0x10000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT (28U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT)

/*
 * TX_PHY0_TX0_BIST_EN (RW)
 *
 * tx phy0 tx0_bist_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK (0x8000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT (27U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT)

/*
 * TX_PHY0_TXCK_LPBK_EN (RW)
 *
 * tx_phy0 txck_lpbk_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK (0x4000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT (26U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT)

/*
 * TX_PHY0_TX3_LPBK_EN (RW)
 *
 * tx_phy0 tx3_lpbk_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK (0x2000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT (25U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT)

/*
 * TX_PHY0_TX2_LPBK_EN (RW)
 *
 * tx_phy0 tx2_lpbk_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK (0x1000000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT (24U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT)

/*
 * TX_PHY0_TX1_LPBK_EN (RW)
 *
 * tx_phy0 tx1_lpbk_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK (0x800000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT (23U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT)

/*
 * TX_PHY0_TX0_LPBK_EN (RW)
 *
 * tx_phy0 tx0_lpbk_en
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK (0x400000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT (22U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT)

/*
 * TX_PHY0_TXCK_PAT_SEL (RW)
 *
 * tx phy0 txck_pat_sel
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK (0x300000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT (20U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT)

/*
 * TX_PHY0_TX3_PAT_SEL (RW)
 *
 * tx phy0 tx3_pat_sel
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK (0xC0000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT (18U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT)

/*
 * TX_PHY0_TX2_PAT_SEL (RW)
 *
 * tx phy0 tx2_pat_sel
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK (0x30000UL)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT (16U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT)

/*
 * TX_PHY0_TX1_PAT_SEL (RW)
 *
 * tx phy0 tx1_pat_sel
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK (0xC000U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT (14U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT)

/*
 * TX_PHY0_TX0_PAT_SEL (RW)
 *
 * tx phy0 tx0_pat_sel
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK (0x3000U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT (12U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT)

/*
 * TX_PHY0_DSI0_PRBS_DISABLE (RW)
 *
 * tx phy0 dsi0_prbs_disable
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK (0x800U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT (11U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT)

/*
 * TX_PHY0_DSI0_PRBS_START (RW)
 *
 * tx phy0 dsi0_prbs_start
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK (0x400U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT (10U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT)

/*
 * TX_PHY0_CKPHY_CTL (RW)
 *
 * tx phy0 ckphy_ctl
 */
#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK (0x1FFU)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT (0U)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK)
#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT)

/* Bitfield definition for register: GPR_WR_D5 */
/*
 * TX_PHY1_PORT_PLL_RDY_SEL (RW)
 *
 * tx phy1 port_pll_rdy_sel
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK (0x20000000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT (29U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT)

/*
 * TX_PHY1_RATE_LVDS (RW)
 *
 * tx phy1 rate_lvds
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK (0x18000000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT (27U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT)

/*
 * TX_PHY1_PHY_MODE (RW)
 *
 * tx phy1 phy_mode
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK (0x6000000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT (25U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT)

/*
 * TX_PHY1_REFCLK_DIV (RW)
 *
 * tx phy1 refclk_div
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK (0xF00000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT (20U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT)

/*
 * TX_PHY1_IDDQ_EN (RW)
 *
 * tx phy1 iddq_en
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (0x80000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT (19U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT)

/*
 * TX_PHY1_RESET_N (RW)
 *
 * tx phy1 reset, active low
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK (0x40000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT (18U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT)

/*
 * TX_PHY1_SHUTDOWNZ (RW)
 *
 * tx phy1 shutdownz, active low
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK (0x20000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT (17U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT)

/*
 * TX_PHY1_BYPS_CKDET (RW)
 *
 * tx phy1 byps_ckdet
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK (0x10000UL)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT (16U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT)

/*
 * TX_PHY1_PLL_DIV (RW)
 *
 * tx phy1 pll_div
 */
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK (0x7FFFU)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT (0U)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK)
#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT)

/* Bitfield definition for register: GPR_WR_D6 */
/*
 * TX_PHY1_PLL_CTRL (RW)
 *
 * tx phy1 pll_ctrl
 */
#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK (0xFFFFFFFFUL)
#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT (0U)
#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK)
#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT)

/* Bitfield definition for register: GPR_WR_D7 */
/*
 * TX_PHY1_TXCK_BIST_EN (RW)
 *
 * tx phy1 txck_bist_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK (0x80000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT (31U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT)

/*
 * TX_PHY1_TX3_BIST_EN (RW)
 *
 * tx phy1 tx3_bist_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK (0x40000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT (30U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT)

/*
 * TX_PHY1_TX2_BIST_EN (RW)
 *
 * tx phy1 tx2_bist_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK (0x20000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT (29U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT)

/*
 * TX_PHY1_TX1_BIST_EN (RW)
 *
 * tx phy1 tx1_bist_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK (0x10000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT (28U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT)

/*
 * TX_PHY1_TX0_BIST_EN (RW)
 *
 * tx phy1 tx0_bist_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK (0x8000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT (27U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT)

/*
 * TX_PHY1_TXCK_LPBK_EN (RW)
 *
 * tx_phy1 txck_lpbk_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK (0x4000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT (26U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT)

/*
 * TX_PHY1_TX3_LPBK_EN (RW)
 *
 * tx_phy1 tx3_lpbk_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK (0x2000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT (25U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT)

/*
 * TX_PHY1_TX2_LPBK_EN (RW)
 *
 * tx_phy1 tx2_lpbk_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK (0x1000000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT (24U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT)

/*
 * TX_PHY1_TX1_LPBK_EN (RW)
 *
 * tx_phy1 tx1_lpbk_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK (0x800000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT (23U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT)

/*
 * TX_PHY1_TX0_LPBK_EN (RW)
 *
 * tx_phy1 tx0_lpbk_en
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK (0x400000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT (22U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT)

/*
 * TX_PHY1_TXCK_PAT_SEL (RW)
 *
 * tx phy1 txck_pat_sel
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK (0x300000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT (20U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT)

/*
 * TX_PHY1_TX3_PAT_SEL (RW)
 *
 * tx phy1 tx3_pat_sel
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK (0xC0000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT (18U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT)

/*
 * TX_PHY1_TX2_PAT_SEL (RW)
 *
 * tx phy1 tx2_pat_sel
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK (0x30000UL)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT (16U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT)

/*
 * TX_PHY1_TX1_PAT_SEL (RW)
 *
 * tx phy1 tx1_pat_sel
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK (0xC000U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT (14U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT)

/*
 * TX_PHY1_TX0_PAT_SEL (RW)
 *
 * tx phy1 tx0_pat_sel
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK (0x3000U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT (12U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT)

/*
 * TX_PHY1_DSI0_PRBS_DISABLE (RW)
 *
 * tx phy1 dsi0_prbs_disable
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK (0x800U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT (11U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT)

/*
 * TX_PHY1_DSI0_PRBS_START (RW)
 *
 * tx phy1 dsi0_prbs_start
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK (0x400U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT (10U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT)

/*
 * TX_PHY1_CKPHY_CTL (RW)
 *
 * tx phy1 ckphy_ctl
 */
#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK (0x1FFU)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT (0U)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK)
#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT)

/* Bitfield definition for register: GPR_WR_D8 */
/*
 * RX_PHY0_BRUN_IN_MODE (RW)
 *
 * rx phy0 burn_in_mode
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK (0x80000000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT (31U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT)

/*
 * RX_PHY0_BURN_IN_EN_PAD (RW)
 *
 * rx phy0 burn_in_en_pad
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK (0x40000000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT (30U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT)

/*
 * RX_PHY0_LPBK_MODE (RW)
 *
 * rx phy0 lpbk_mode
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK (0x30000000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT (28U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT)

/*
 * RX_PHY0_BIST_FREQ_TRIM (RW)
 *
 * rx phy0 bist_freq_trim
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK (0xF000000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT (24U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT)

/*
 * RX_PHY0_RX0_BIST_EN (RW)
 *
 * rx phy0 rx0_bist_en rx1_bist_en
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK (0x400000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT (22U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT)

/*
 * RX_PHY0_BIST_MODE (RW)
 *
 * rx phy0 bist_mode
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK (0x200000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT (21U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT)

/*
 * RX_PHY0_BIST_EN_PAD (RW)
 *
 * rx phy0 bist_en_pad
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK (0x100000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT (20U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT)

/*
 * RX_PHY0_BIST_EN (RW)
 *
 * rx phy0 bist_en
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK (0x80000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT (19U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT)

/*
 * RX_PHY0_BIST_CKIN_SEL (RW)
 *
 * rx phy0 bist_ckin_sel
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK (0x40000UL)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT (18U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT)

/*
 * RX_PHY0_PHY_MODE (RW)
 *
 * rx phy0 phy_mode
 */
#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK (0x3U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT (0U)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK)
#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT)

/* Bitfield definition for register: GPR_WR_D9 */
/*
 * RX_PHY1_BRUN_IN_MODE (RW)
 *
 * rx phy1 burn_in_mode
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK (0x80000000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT (31U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT)

/*
 * RX_PHY1_BURN_IN_EN_PAD (RW)
 *
 * rx phy1 burn_in_en_pad
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK (0x40000000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT (30U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT)

/*
 * RX_PHY1_LPBK_MODE (RW)
 *
 * rx phy1 lpbk_mode
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK (0x30000000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT (28U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT)

/*
 * RX_PHY1_BIST_FREQ_TRIM (RW)
 *
 * rx phy1 bist_freq_trim
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK (0xF000000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT (24U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT)

/*
 * RX_PHY1_RX0_BIST_EN (RW)
 *
 * rx phy1 rx0_bist_en rx1_bist_en
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK (0x400000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT (22U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT)

/*
 * RX_PHY1_BIST_MODE (RW)
 *
 * rx phy1 bist_mode
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK (0x200000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT (21U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT)

/*
 * RX_PHY1_BIST_EN_PAD (RW)
 *
 * rx phy1 bist_en_pad
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK (0x100000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT (20U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT)

/*
 * RX_PHY1_BIST_EN (RW)
 *
 * rx phy1 bist_en
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK (0x80000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT (19U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT)

/*
 * RX_PHY1_BIST_CKIN_SEL (RW)
 *
 * rx phy1 bist_ckin_sel
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK (0x40000UL)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT (18U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT)

/*
 * RX_PHY1_PHY_MODE (RW)
 *
 * rx phy1 phy_mode
 */
#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK (0x3U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT (0U)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK)
#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT)

/* Bitfield definition for register: GPR_RO_D0 */
/*
 * TX_PHY1_CTL_O (RO)
 *
 * {2'b0,
 * tx_phy1_tx3_ctl_o,tx_phy1_tx2_ctl_o,
 * tx_phy1_tx1_ctl_o,tx_phy1_tx0_ctl_o,
 * tx_phy1_txck_ctl_o,tx_phy1_pll_dtest_o}
 */
#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK (0xFF00U)
#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT (8U)
#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT)

/*
 * TX_PHY0_CTL_O (RO)
 *
 * {2'b0,
 * tx_phy0_tx3_ctl_o,tx_phy0_tx2_ctl_o,
 * tx_phy0_tx1_ctl_o,tx_phy0_tx0_ctl_o,
 * tx_phy0_txck_ctl_o,tx_phy0_pll_dtest_o}
 */
#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK (0xFFU)
#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT (0U)
#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT)

/* Bitfield definition for register: GPR_RO_D1 */
/*
 * IRQ_CSI0_AP (RO)
 *
 * interrupt of csi0 ap
 */
#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK (0x20000UL)
#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT (17U)
#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK) >> PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT)

/*
 * CSI0_CFG_CSI_AP_DIAG_FAULTS (RO)
 *
 * csi0 ap diag faults
 */
#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL)
#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U)
#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT)

/*
 * CSI0_STA_AP_IF_INT_STA (RO)
 *
 * csi0 apb parity check interrupt satus
 */
#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK (0x1FU)
#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT (0U)
#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT)

/* Bitfield definition for register: GPR_RO_D2 */
/*
 * IRQ_CSI1_AP (RO)
 *
 * interrupt of csi1 ap
 */
#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK (0x20000UL)
#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT (17U)
#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK) >> PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT)

/*
 * CSI1_CFG_CSI_AP_DIAG_FAULTS (RO)
 *
 * csi1 ap diag faults
 */
#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL)
#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U)
#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT)

/*
 * CSI1_STA_AP_IF_INT_STA (RO)
 *
 * csi1 apb parity check interrupt satus
 */
#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK (0x1FU)
#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT (0U)
#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT)

/* Bitfield definition for register: GPR_RO_D3 */
/*
 * RX_PHY0_RXCK_CTLO (RO)
 *
 * rx phy0 rxck_ctlo
 */
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK (0xFF00U)
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT (8U)
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT)

/*
 * RX_PHY0_RX1_CTLO (RO)
 *
 * rx phy0 rx1_ctlo
 */
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK (0xF0U)
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT (4U)
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT)

/*
 * RX_PHY0_RX0_CTLO (RO)
 *
 * rx phy0 rx0_ctlo
 */
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK (0xFU)
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT (0U)
#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT)

/* Bitfield definition for register: GPR_RO_D4 */
/*
 * RX_PHY1_RXCK_CTLO (RO)
 *
 * rx phy1 rxck_ctlo
 */
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK (0xFF00U)
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT (8U)
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT)

/*
 * RX_PHY1_RX1_CTLO (RO)
 *
 * rx phy1 rx1_ctlo
 */
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK (0xF0U)
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT (4U)
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT)

/*
 * RX_PHY1_RX0_CTLO (RO)
 *
 * rx phy1 rx0_ctlo
 */
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK (0xFU)
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT (0U)
#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT)

/* Bitfield definition for register: GPR_RO_D5 */
/*
 * DSI0_PRBS_STATE (RO)
 *
 * dsi0_prbs_state for debug only
 */
#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK (0xF000U)
#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT (12U)
#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT)

/*
 * TX_PHY0_TXCK_BIST_DONE_PAD (RO)
 *
 * tx phy0 txck_done_pad
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK (0x800U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT (11U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT)

/*
 * TX_PHY0_TXCK_BIST_OK_PAD (RO)
 *
 * tx phy0 txck_ok_pad
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK (0x400U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT (10U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT)

/*
 * TX_PHY0_TXCK_BIST_DONE (RO)
 *
 * tx phy0 txck_bist_done
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK (0x200U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT (9U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT)

/*
 * TX_PHY0_TX3_BIST_DONE (RO)
 *
 * tx phy0 tx3_bist_done
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK (0x100U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT (8U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT)

/*
 * TX_PHY0_TX2_BIST_DONE (RO)
 *
 * tx phy0 tx2_bist_done
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK (0x80U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT (7U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT)

/*
 * TX_PHY0_TX1_BIST_DONE (RO)
 *
 * tx phy0 tx1_bist_done
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK (0x40U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT (6U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT)

/*
 * TX_PHY0_TX0_BIST_DONE (RO)
 *
 * tx phy0 tx0_bist_done
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK (0x20U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT (5U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT)

/*
 * TX_PHY0_TXCK_BIST_OUT (RO)
 *
 * tx phy0 txck_bist_out
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK (0x10U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT (4U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT)

/*
 * TX_PHY0_TX3_BIST_OUT (RO)
 *
 * tx phy0 tx3_bist_out
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK (0x8U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT (3U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT)

/*
 * TX_PHY0_TX2_BIST_OUT (RO)
 *
 * tx phy0 tx2_bist_out
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK (0x4U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT (2U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT)

/*
 * TX_PHY0_TX1_BIST_OUT (RO)
 *
 * tx phy0 tx1_bist_out
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK (0x2U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT (1U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT)

/*
 * TX_PHY0_TX0_BIST_OUT (RO)
 *
 * tx phy0 tx0_bist_out
 */
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK (0x1U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT (0U)
#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT)

/* Bitfield definition for register: GPR_RO_D6 */
/*
 * DSI1_PRBS_STATE (RO)
 *
 * dsi1_prbs_state for debug only
 */
#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK (0xF000U)
#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT (12U)
#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT)

/*
 * TX_PHY1_TXCK_BIST_DONE_PAD (RO)
 *
 * tx phy1 txck_done_pad
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK (0x800U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT (11U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT)

/*
 * TX_PHY1_TXCK_BIST_OK_PAD (RO)
 *
 * tx phy1 txck_ok_pad
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK (0x400U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT (10U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT)

/*
 * TX_PHY1_TXCK_BIST_DONE (RO)
 *
 * tx phy1 txck_bist_done
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK (0x200U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT (9U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT)

/*
 * TX_PHY1_TX3_BIST_DONE (RO)
 *
 * tx phy1 tx3_bist_done
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK (0x100U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT (8U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT)

/*
 * TX_PHY1_TX2_BIST_DONE (RO)
 *
 * tx phy1 tx2_bist_done
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK (0x80U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT (7U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT)

/*
 * TX_PHY1_TX1_BIST_DONE (RO)
 *
 * tx phy1 tx1_bist_done
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK (0x40U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT (6U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT)

/*
 * TX_PHY1_TX0_BIST_DONE (RO)
 *
 * tx phy1 tx0_bist_done
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK (0x20U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT (5U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT)

/*
 * TX_PHY1_TXCK_BIST_OUT (RO)
 *
 * tx phy1 txck_bist_out
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK (0x10U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT (4U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT)

/*
 * TX_PHY1_TX3_BIST_OUT (RO)
 *
 * tx phy1 tx3_bist_out
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK (0x8U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT (3U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT)

/*
 * TX_PHY1_TX2_BIST_OUT (RO)
 *
 * tx phy1 tx2_bist_out
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK (0x4U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT (2U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT)

/*
 * TX_PHY1_TX1_BIST_OUT (RO)
 *
 * tx phy1 tx1_bist_out
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK (0x2U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT (1U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT)

/*
 * TX_PHY1_TX0_BIST_OUT (RO)
 *
 * tx phy1 tx0_bist_out
 */
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK (0x1U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT (0U)
#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT)

/* Bitfield definition for register: GPR_RO_D7 */
/*
 * RX_PHY0_BURN_IN_OK_PAD (RO)
 *
 * rx_phy0_burn_in_ok_pad
 */
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK (0x40U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT (6U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT)

/*
 * RX_PHY0_RX1_BIST_DONE (RO)
 *
 * rx phy0 rx1_bist_done
 */
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK (0x20U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT (5U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT)

/*
 * RX_PHY0_RX0_BIST_DONE (RO)
 *
 * rx phy0 rx0_bist_done
 */
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK (0x10U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT (4U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT)

/*
 * RX_PHY0_RX1_BIST_OUT (RO)
 *
 * rx phy0 rx1_bist_out
 */
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK (0x8U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT (3U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT)

/*
 * RX_PHY0_RX0_BIST_OUT (RO)
 *
 * rx phy0 rx0_bist_out
 */
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK (0x4U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT (2U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT)

/*
 * RX_PHY0_BIST_OK_PAD (RO)
 *
 * rx phy0 bist_ok_pad
 */
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK (0x2U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT (1U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT)

/*
 * RX_PHY0_BIST_DONE_PAD (RO)
 *
 * rx phy0 bist_done_pad
 */
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK (0x1U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT (0U)
#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT)

/* Bitfield definition for register: GPR_RO_D8 */
/*
 * RX_PHY1_BURN_IN_OK_PAD (RO)
 *
 * rx_phy1_burn_in_ok_pad
 */
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK (0x40U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT (6U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT)

/*
 * RX_PHY1_RX1_BIST_DONE (RO)
 *
 * rx phy1 rx1_bist_done
 */
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK (0x20U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT (5U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT)

/*
 * RX_PHY1_RX0_BIST_DONE (RO)
 *
 * rx phy1 rx0_bist_done
 */
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK (0x10U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT (4U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT)

/*
 * RX_PHY1_RX1_BIST_OUT (RO)
 *
 * rx phy1 rx1_bist_out
 */
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK (0x8U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT (3U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT)

/*
 * RX_PHY1_RX0_BIST_OUT (RO)
 *
 * rx phy1 rx0_bist_out
 */
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK (0x4U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT (2U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT)

/*
 * RX_PHY1_BIST_OK_PAD (RO)
 *
 * rx phy1 bist_ok_pad
 */
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK (0x2U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT (1U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT)

/*
 * RX_PHY1_BIST_DONE_PAD (RO)
 *
 * rx phy1 bist_done_pad
 */
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK (0x1U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT (0U)
#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT)

/* Bitfield definition for register: GPR_RO_D9 */
/* Bitfield definition for register: GPR_WR1_CLR_D0 */
/*
 * GPR_WR1_CLR_DATA (RW)
 *
 * gpr register, write 1 /no-write  set/clr matching bit
 */
#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK (0xFFFFFFFFUL)
#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT (0U)
#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK)
#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) >> PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT)



/* DSI_SETTING register group index macro definition */
#define PIXELMUX_DSI_SETTING_DSI0_CFG (0UL)
#define PIXELMUX_DSI_SETTING_DSI1_CFG (1UL)


#endif /* HPM_PIXELMUX_H */
